When it comes to the ESD protection of high speed pads, e.g. I/O pads for radio frequency (RF) circuits such as operational amplifiers and ESD protection device with low parasitic capacitance is required.
Current solutions for providing ESD protection diodes is to provide standard diffusion CMOS diodes involving a p-n junction between an n+ region and a p-well or between a p+ region and an n-well. However, these devices cannot be implemented in a pure bipolar process. Also, they involve a large junction area with correspondingly high parasitic capacitance.
A simplified circuit diagram of a prior art ESD protection network for differential amplifiers is shown in FIG. 1 and includes the differential amplifiers 100, 102 with their outputs 104, 106, respectively. ESD protection diode 110 is connected between the VDD power supply rail and input pad 112, while diode 114 is connected between the input pad 112 and ground. Similarly, diode 120 is connected between the VDD power supply rail and input pad 122, while diode 124 is connected between the input pad 122 and ground. The outputs 104, 106 are similarly protected by diodes 130, 132 and 140, 142, respectively, as shown. The circuit also includes a BSCR clamp 150 connected between the VDD power supply rail and ground for protecting against electrostatic discharges (ESD) across the power supply rails.
The current application proposes the creation of an ESD protection diode making use of a poly-emitter BJT that addresses some of the problems with prior art diffusion diodes.